Power-on reset circuit

ABSTRACT

A power-on reset circuit is capable of outputting a normal reset signal despite slow rise of power supply voltage. A node is interposed between a MOS capacitor including a PMOS with its drain and source connected in common and an NMOS having its gate fixedly connected to a ground potential. The node is connected to a ground potential via the NMOS and also to a power supply line via the MOS capacitor. Therefore, even when the power supply voltage rises slowly after power is turned on, the potential of the node rises substantially at the same rate as the power supply voltage. After the power supply voltage reaches a predetermined power supply potential, the potential of the node is gradually lowered due to an off leakage current through the NMOS. The node is connected with an inverter operating according to the power supply voltage. When the potential of the node decreases below ½ of the power supply voltage, the reset signal outputted from the inverter goes to the H level.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a power-on reset circuit for generatinga reset signal for initializing a system while being connected to apower source.

2. Related Art

As a conventional power-on reset circuit, there is a known one disclosedin Japanese Patent Kokai No. 10-163840, for example. FIGS. 1A and 1Bthere in are diagrams explaining the power-on reset circuit. FIG. 1Ashows a circuit configuration whereas FIG. 1B shows operation waveforms.

As shown in FIG. 1A, the power-on reset circuit includes N-channel MOStransistors 1, 2 (hereinafter, a MOS transistor will be referred tosimply as MOS while an N-channel MOS will be referred to simply as NMOS)which are connected in series between a node NA and a ground potentialGND. The NMOS s 1, 2 each have its gate connected to a power supply line10 so as to be supplied with a power supply voltage VD. Connectedbetween the node NA and the power supply line 10 is a MOS capacitor 3utilizing capacitance between the gate and source/drain of a P-channelMOS (hereinafter, referred to as PMOS). Specifically, the gate of thePMOS is connected to the node NA whereas the source and drain thereofare connected to the power supply line 10.

On the other hand, the node NA is connected with an input of an inverter4, the output of which is connected with a node NB. Connected betweenthe node NB and a ground potential GND is a MOS capacitor 5 utilizingcapacitance between the gate and source/drain of an NMOS. Specifically,the gate of the NMOS is connected to the node NB whereas the source anddrain thereof are connected to a ground potential GND.

The node NB is further connected with inverters 6, 7 in cascade. A resetsignal POR is outputted from the inverter 7 and applied to the circuitblock to be reset. Although not shown in the figure, an arrangement ismade such that the power supply voltage VD power source is supplied tothe inverters 4, 6, 7 and the circuit block via the power supply line10.

Next, operations of the power-on reset circuit will be described.

Prior to the power-on transition, the power supply voltage VD is at 0Vand hence, the nodes NA, NB are at the ground potential GND so that theMOS capacitors 3, 5 store no electric charges. Therefore, the MOScapacitors 3, 5 each have a terminal-to-terminal voltage of 0V. When thepower is applied at time t0 as shown in FIG. 1B, the power supplyvoltage VD on the power supply line 10 starts rising from 0V to apredetermined power supply potential VDD.

Immediately after the power is turned on, when the power supply voltageVD is below the threshold voltage VTN of the NMOS s 1, 2, these NMOS s1, 2 are OFF and the node NA is connected to the power supply line 10via the MOS capacitor 3 whose terminal-to-terminal voltage is 0V. Hence,by charge conservation, the potential VA of the node NA will beincreased in the same manner as the power supply voltage VD.

At time t1 when the power supply voltage VD exceeds the thresholdvoltage VTN, the NMOSs 1, 2 have their gates connected to the powersupply line 10 and so are turned ON. This permits a current to flow fromthe node NA to the ground potential GND via the NMOSs 1, 2. Accordingly,the subsequent fluctuation of the potential VA is greatly affected bythe rate of increase of the power supply voltage VD, the on resistance(drive current capability) of the NMOSs 1, 2 and the capacity of the MOScapacitor 3. That is, if the power supply voltage VD rises fast, the MOScapacitor 3 has a large capacity and the NMOSs 1, 2 has large onresistances, the increase of potential VA follows closely the increasein the power supply voltage VD, albeit at a lower rate.

From time t2 when the power supply voltage VD reaches the predeterminedpower supply potential VDD, the potential VA exponentially falls inaccordance with the time constant of the on resistance of the NMOSs 1, 2and the time constants of the capacitance of NMOS 3. At time t3 when thepotential VA of the node NA decreases below ½ of the power supplyvoltage VD, the output signal from the inverter 4 connected with thenode NA is shifted from L level to H level. Since the MOS capacitor 5 isconnected between the node NB on the output side of the inverter 4 andthe ground potential GND, the potential VB of the node NB rises from theground potential GND to the power supply potential VDD in accordancewith a given time constant.

At time t4 when the potential VB of the node NB rises to above ½ of thepower supply voltage VD, the output from the inverter 6 connected withthe node NB is inverted and the output from the inverter 7 connected incascade with the inverter 6 is also inverted, thereafter applied as thereset signal POR to the circuit block.

However, the aforesaid power-on reset circuit has the preconditions thatthe power supply voltage VD rises fast, the MOS capacitor 3 has largecapacity, and the on resistances of the NMOSs 1, 2 are large, so thatthe potential VA of the node NA continues to rise after the NMOSs 1, 2are turned ON.

Hence, the following problem may be encountered in the following case.If when the power is turned on, the rise of the power supply voltage VDis slow, the potential VA of the node NA may rise very little or evenstart falling after the NMOSs 1, 2 are turned ON. In such cases, thenode NA stays at L level from the start and remains unchanged, whereasthe node NB stays at H level and remains unchanged. Therefore, the resetsignal POR assumes H level from the start, disabling normal resettingoperations.

To cope with this slow rise of the power supply voltage VD withoutchanging circuit configuration, the gate lengths of the NMOSs 1, 2 needto be increased so as to increase the on resistances thereof, or toincrease the gate area of the PMOS gate so as to increase the capacityof the MOS capacitor 3. This results in an undesirable increase in areaof the circuit pattern.

It is an object of the invention to provide a power-on reset circuitcapable of outputting a normal reset signal POR despite the slow rise ofthe power supply voltage VD.

SUMMARY OF THE INVENTION

According to a first aspect of the invention, the power-on reset circuitcomprises: a capacitor connected between a power supply line and aninternal node; a MOS transistor having its drain connected to theinternal node and its source connected to a reference potential, and setin OFF state; and an output portion outputting a reset signal when thepotential of the internal node decreases below the threshold voltageafter the application of a power supply voltage to the power supplyline.

According to a second aspect of the invention, the power-on resetcircuit comprises: a first capacitor connected between a power supplyline and a first node; a first MOS transistor which is ON/OFF controlledbased on a first pulse signal and connected between the first node and asecond node; a second MOS transistor which is ON/OFF controlled based ona second pulse signal and connected between the second node and areference potential; a second capacitor connected between the secondnode and the reference potential; a timing control unit for generatingthe first and second pulse signals in synchronism with a clock signalexternally applied thereto; and an output portion outputting a resetsignal when the potential of the internal node decreases below athreshold voltage after the application of a power supply voltage to thepower supply line.

According to the first aspect of the invention, the power-on resetcircuit is configured so that the internal node is connected to thereference potential via an MOS normally set in the OFF state. Thisprovides an effect that the circuit is capable of outputting a normalreset signal despite the slow rise of the power supply voltage becausethe internal node follows closely the change in power supply voltage.

According to the other aspect of the invention, the power-on resetcircuit comprises a timing control unit providing ON/OFF control insynchronism with the clock signal, thereby switching ON or OFF the firstand second MOSs serially connected between the first node and thereference potential. In addition to the advantage offered by thepower-on reset circuit of the first aspect, an advantage is providedthat the power-on reset signal synchronized with the clock signal can beoutputted. These and other objects, and novel features of the inventionwill become fully apparent from the following description thereof takenin conjunction with the accompanying drawings which illustrate preferredembodiments of the invention. It is to be noted, however, that thedrawings are for purposes of illustration only and do not limit thescope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are diagrams illustrating a conventional power-on resetcircuit;

FIGS. 2A and 2B are diagrams illustrating a power-on reset circuitaccording to Example 1 of the invention;

FIG. 3 is a circuit diagram illustrating a power-on reset circuitaccording to Example 2 of the invention;

FIGS. 4A and 4B are diagrams illustrating a power-on reset circuitaccording to Example 3 of the invention; and

FIGS. 5A and 5B are diagrams illustrating a power-on reset circuitaccording to Example 4 of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 2A and 2B illustrate a power-on reset circuit according to Example1 of the invention. FIG. 2A shows a circuit configuration whereas FIG.2B shows operation waveforms.

As shown in FIG. 2A, the power-on reset circuit includes an NMOS 11connected between a node NX and a ground potential GND. The NMOS 11 hasits gate connected to the ground potential GND. Connected between theNode NX and a power supply line 10 is a MOS capacitor 12 utilizingcapacitance between the gate and source/drain of a PMOS. Specifically,the PMOS has its gate connected to the node NX and its source and drainconnected to the power supply line 10. The node NX is further connectedwith three inverter stages 13, 14, 15 in cascade. A reset signal POR isoutputted from the final inverter stage 15, and applied to the circuitblock to be reset. Although not shown in the figure, an arrangement ismade so that a power supply voltage VD is supplied to the inverters13-15 and the circuit block via the power supply line 10. Next,operations of the power-on reset circuit will be described.

Prior to turning on power, the power supply voltage VD is 0V and hence,a potential VX of the node NX is the ground potential GND so that noelectric charge is stored in the MOS capacitor 12. Therefore, the MOScapacitor 12 has a terminal-to-terminal voltage of 0V. On the otherhand, the NMOS 11 has its gate fixedly connected with the groundpotential GND and hence, the NMOS 11 is in OFF state.

When the power is turned on at time t10 as shown in FIG. 2B, the powersupply voltage VD on the power supply line 10 starts rising from 0V to apredetermined power supply potential VDD. Since the NMOS 11 is always inOFF state, no current except for a small leakage current (off leakagecurrent) flows through the NMOS 11. The node NX is connected to thepower supply line 10 via the MOS capacitor 12 with terminal-to-terminalvoltage 0V. Hence, the potential VX of the node NX rises due to chargeconservation just as the power supply voltage VD does.

The inverter 13 connected with the node NX is supplied with the powersupply voltage VD. The input level of the inverter 13 is the potentialVX which in turn is substantially equal to the power supply voltage. VD.Hence, an output signal from the inverter 13 is at L level. Accordingly,the reset signal POR outputted from the inverter 15 is also at L level.Thus, the circuit block is set to an initial state.

At time t11 when the power supply voltage VD reaches the predeterminedpower supply potential VDD, the potential VX of the node NX also reachesa level substantially equal to the power supply potential VDD.Subsequently, the potential VX exponentially falls in accordance with atime constant determined by large off leakage resistance of the NMOS 11and the MOS capacitor 12.

At time t12 when the potential VX of the node NX decreases below ½ ofthe power supply voltage VD, the output signal S13 from the inverter 13connected with the node NX is shifted from L level to H level. Thus theoutput signal from the inverter 14 is inverted and so is the outputsignal from the inverter 15 connected in cascade with the inverter 14.Thus, the reset signal POR is shifted to H level and applied to thecircuit block. This releases the circuit block from the initial state sothat predetermined operations are started.

As described above, the power-on reset circuit of Example 1 is soconfigured as to provide timing to shift the reset signal POR from Llevel to H level in accordance with the time constant determined fromthe off-leakage resistance of the NMOS 11 and from the MOS capacitor 12.This leads to an advantage that despite slow rise of the power supplyvoltage VD, the power-on circuit is capable of outputting the normalreset signal POR without increasing the area of the circuit pattern.

FIG. 3 is a circuit diagram illustrating a power-on reset circuitaccording to Example 2 of the invention. In the figure, componentssimilar to those shown in FIG. 2A are represented by the same referencecharacters, respectively.

The power-on reset circuit is characterized by imparting hysteresis tothe output of the power-on reset circuit of FIG. 2A. Specifically, aPMOS 16 is added, and its drain, gate and source are connected to theoutput of the inverter 13 (or the input of the inverter 14), the outputof the inverter 14 (or the input of the inverter 15) and the powersupply line 10, respectively. Otherwise, the circuit is configured thesame way as that of FIG. 2A. Since basic operations of the power-onreset circuit are the same as those illustrated in FIG. 2B, a detaileddescription thereof is dispensed with. In short, when the potential ofthe node NX decreases below the threshold voltage of the inverter 11,the output signal from the inverter 13 is shifted from L level to Hlevel. Thus, the output signal from the inverter 14 is shifted from Hlevel to L level so that PMOS 16 is turned ON.

At this time, the potential of the node NX is lower than the thresholdvoltage of the inverter 13, and thus is recognized as being at the Llevel. However, the potential of the node NX is not as low as the groundpotential GND. On the other hand, the potential at the output of theinverter 13 is recognized as H level but is actually at an intermediatepotential. Therefore, the inverter is in an instable condition. If, inthis state, the PMOS 16 is turned ON, the inverter is increased inpotential to be shifted to a stable H level because the input of theinverter 14 is connected with the power supply line 10 via the PMOS 16.

As described above, the power-on reset circuit of Example 2 includes theadditional PMOS 16 for imparting the hysteresis characteristic to theoutput portion thereof. This leads to an advantage of preventing thereset signal POR from being affected by noises which may occur when thenode NX is shifted from H level to L level. Thus, the circuit canaccomplish more stable operations.

FIGS. 4A and 4B are diagrams illustrating a power-on reset circuitaccording to Example 3 of the invention. FIG. 4A shows a circuitconfiguration and FIG. 4B shows operation waveforms. In FIG. 4A,components similar to those shown in FIG. 3A are represented by the samereference characters, respectively.

The power-on reset circuit is adapted to generate a reset signalsynchronized with a clock signal applied by an external device. As shownin FIG. 4A, the circuit includes series-connected NMOSs 17, 18 in placeof the NMOS 11 shown in FIG. 3, and a timing control unit 20 forcontrolling these NMOSs 17, 18.

A capacitor 19 has one end connected to a junction point (node NY)between the source of the NMOS 17 and the drain of the NMOS 18. Theother end of the capacitor 19 is connected to the ground potential GND.The timing control unit 20 has a terminal 21 to which a clock signal CLKis applied by the external device. Three inverter stages 22-24 areconnected in cascade with the terminal 21. The final inverter stage 24has its output connected to one of the two inputs of a NOT-AND gate 25(hereinafter, referred to as NAND). The other input of the NAND 25 isconnected to the terminal 21. A signal S25 outputted from the NAND 25 isapplied to a gate of the NMOS 18 and also is inverted by the inverter 26so as to be converted to a signal S26, which is applied to a gate of theNMOS 17.

When the clock signal CLK alternating between L level and H level with agiven period is applied to the terminal 21, the timing control unit 20outputs the pulse signals S25, S26 in synchronism with the rise of theclock signal CLK, the L level pulse signal S25 outputted during thedelay time of the inverters 22-24, and the pulse signal S26 being aninverted version of the signal S25. Otherwise, the circuit is configuredthe same way as that of FIG. 3. Next, operations of the power-on resetcircuit will be described.

When the power-on reset circuit is not supplied with the clock signalCLK (that is, fixed to L or H level), the signal S25 outputted from theNAND 25 of the timing control unit 20 is at H level whereas the signalS26 outputted from the inverter 26 is at L level. Accordingly, the NMOSs17, 18 are in OFF state and in ON state, respectively, and hence, thesame configuration as that of FIG. 3 is established so as to performsimilar operations. When supplied with the clock signal CLK, the circuitoperates as follows.

When the power is applied at time t20 as shown in FIG. 4B, the powersupply voltage VD on the power supply line 10 starts rising from 0V to apredetermined power supply potential VDD. If the clock signal CLK is atL level when power is applied, the signals S25, S26 are at H level and Llevel, respectively, and hence, the NMOSs 17, 18 are in OFF state and inON state, respectively. Therefore, no current except for a small leakagecurrent (off leakage current) flows through the NMOS 17.

The node NX is connected to the power supply line 10 via the MOScapacitor 12 having terminal-to-terminal voltage of 0V. Hence, thepotential VX of the node NX rises due to charge conservation the sameway as the power supply voltage VD does. On the other hand, the NMOS 18is in ON state so that a potential VY of the node NY is substantiallyequal to the ground potential GND.

At time t21 when the power supply voltage VD reaches a predeterminedpower supply potential VDD, the potential VX of the node NX also reachesa level substantially equal to the power supply potential VDD.Subsequently, the potential VX exponentially falls in accordance with alarge time constant determined from the large off leakage resistance ofthe NMOS 11 and from the MOS capacitor 12. However, the drop inpotential is extremely slow.

At time t22 when the clock signal CLK rises, the signals S25, S26outputted from the timing control unit 20 assume L level and H level fora given time period, respectively. This brings the NMOS 17 into ON stateand the NMOS 18 into OFF state. Consequently, the node NX shares theelectric charge with the capacitor 19 connected to the node NY via theNMOS 17. The potential VX of the node NX quickly falls in correspondenceto the amount allocated to the capacitor 19 whereas the potential VY ofthe node NY rises correspondingly.

At time t23 when the signals S25, S26 are returned to H level and Llevel, respectively, the NMOS 17 is turned OFF while the NMOS 18 isturned ON. Thus, the node NX is isolated from the node NY. On the otherhand, the capacitor 19 is discharged via the NMOS 18 so that thepotential VY of the node NY is decreased to the ground potential GND.

At each rise of the clock signal CLK at time t24, t25, the sameoperations as those performed at time t22 are repeated so that thepotential VX of the node NX is decreased stepwise. At time t25 when thepotential VX decreases below ½ of the power supply voltage VD, forexample, the output signal from the inverter 13 connected to the node NXis shifted from L level to H level, thereby shifting the reset signalPOR to H level. The number of clock cycles until the potential VX of thenode NX decreases less than the threshold value of the inverter 13 canbe set by adjusting the capacitance ratio between the MOS capacitor 12and the capacitor 19. As described above, the power-on reset circuit ofExample 3 includes the timing control unit 20 for providing ON/OFFcontrol of the NMOSs 17, 18 in synchronism with the clock signal CLKexternally applied thereto. This permits the potential VX of the node NXto be decreased stepwise according to a given period. In addition to theadvantage offered by Example 2, there is further provided an advantageof outputting the reset signal POR synchronized with the clock signalCLK.

The timing control unit 20 of Example 3 is adapted to turn ON/OFF theNMOSs 17, 18 with the same timing. This involves the following potentialfear. In some timings, the NMOSs 17, 18 may be brought into a temporaryON state at the same time, connecting the node NX to the groundpotential GND. Consequently, the timing control unit may not be able toprovide the programmed timing. Example 4 eliminates such a fear.

FIGS. 5A and 5B are diagrams illustrating a power-on reset circuitaccording to Example 4 of the invention. FIG. 5A shows a circuitconfiguration whereas FIG. 5B shows operation waveforms. In FIG. 5A,components similar to those shown in FIG. 4A are represented by the samereference characters, respectively.

As shown in FIG. 5A, the power-on reset circuit is configured the sameway as the power-on reset circuit of FIG. 4A, except that the timingcontrol unit 20 of FIG. 4A is replaced by a timing control unit 20Ahaving a somewhat different configuration from the above.

The timing control unit 20A further includes inverters 27-30, 32 and aNAND 31 in addition to the terminal 21, inverters 22-24, 26 and NAND 25employed by the timing control unit 20.

Specifically, the terminal 21 is connected with the inverter 27 forinverting the clock signal CLK. The inverter 27 has its output connectedto one of the input terminals of the NAND 31 via the three inverterstages 28-30 connected in cascade, and connected directly to the otherinput terminal of the NAND 31. The output of the NAND 31 is connectedwith the inverter 32, which outputs a signal S32 to the gate of the NMOS18. Next, operations of the power-on reset circuit will be described.

When the power-on reset circuit is not supplied with the clock signalCLK, both the signals S26, S32 outputted from the inverters 26, 32 ofthe timing control unit 20A are at L level. Therefore, both the NMOSs17, 18 are in OFF state so that the same operations as those shown inFIG. 3 are carried out.

When the clock signal CLK is applied, the operations are performed asfollows.

When the power is applied at time t30 as shown in FIG. 5B, the powersupply voltage VD on the power supply line 10 starts rising from 0V to apredetermined potential VDD. If the clock signal is at L level whenpower is turned on, both the signals S26, S32 are at L level. Hence,both the NMOSs 17, 18 are in OFF state so that no current except for asmall leakage current flows therethrough. Since the node NX is connectedto the power supply line 10 via the MOS capacitor 12 having aterminal-to-terminal voltage of 0V, the potential VX of the node NXrises in almost the same way as the power supply voltage VD.

At time t31 when the power supply voltage VD reaches the predeterminedpower supply potential VDD, the potential VX of the node NX also reachesa level substantially equal to the power supply potential VDD.

At time t32 when the clock signal CLK rises, the signal S26 outputtedfrom the timing control unit 20A is at H level for a limited period oftime. This causes the NMOS 17 to be ON whereas the NMOS 18 stays in OFFstate. Consequently, the node NX shares the electric charges with thecapacitor 19 connected to the node NY via the NMOS 17. Hence, thepotential VX of the node NX quickly falls in correspondence to theamount allocated to the capacitor 19 whereas the potential VY of thenode NY rises correspondingly.

At time t33 when the signal S26 is returned to L level, the NMOS 17 isturned OFF so that the node NX is isolated from the node NY. At time t34when the clock signal CLK falls, the signal S32 outputted from thetiming control unit 20A assumes H level for a limited period of time.This switches ON the NMOS 18 whereas the NMOS 17 stays in OFF state.Consequently, the capacitor 19 is discharged via the NMOS 18 so that thepotential VY of the node NY is decreased to the ground potential GND.

At each rise of the clock signal CLK at times t35, t37, the sameoperations as those performed at time t32 are repeated so that thepotential VX of the node NX is lowered stepwise. At each drop of theclock signal CLK at time t36, the same operations as those performed attime t34 are repeated, and the capacitor 19 is discharged.

At a rise of the clock signal CLK such as time t37 when the potential VXdecreases below ½ of the power supply voltage VD, for example, theoutput signal from the inverter 13 connected to the node NX is shiftedfrom L level to H level, thereby shifting the reset signal POR to Hlevel.

As described above, the power-on reset circuit of Example 4 includes thetiming control unit 20A which provides control to turn ON the NMOS 17for a limited period of time in synchronism with the rise of theexternally supplied clock signal CLK, and to turn ON the NMOS 18 for alimited period of time in synchronism with the fall of the clock signalCLK. Thus, the NMOSs 17, 18 are prevented from being turned ON at thesame time so that the fear of bringing the node NX into connection withthe ground potential GND is eliminated. In addition to the advantagesoffered by Example 3, there is further provided an advantage of ensuringstable operations according to design.

It is to be understood that the foregoing examples are mere illustrativeexamples for clarifying the technical details of the invention. Theinvention should not be construed in a narrow sense limited to theforegoing examples but various changes or modifications may be madethereto within a scope of the invention defined by the appended claims.Examples of the modification include as follows:

-   (a) The MOS capacitor 12 based on PMOS is connected between the    power supply line 10 and the node NX. However, the device so    connected is not limited to the MOS capacitor and any capacitor is    applicable.-   (b) While the output portion for the reset signal POR consists of    the three inverter stages 13-15, the configuration of the output    portion is not limited to this.-   (c) Although the delay circuit of the timing control unit 20, 20A is    constituted by the three inverter stages, the number of inverter    stages is optional. Furthermore, an alternative delay circuit may be    used. That is, any circuit configuration that is capable of    generating a pulse signal synchronized with the clock signal may be    applied the same way.

This application is based on Japanese Patent Application No. 2003-384523which is herein incorporated by reference.

1. A power-on reset circuit comprising: a capacitor connected between apower supply line and an internal node; a MOS transistor having itsdrain connected to said internal node and its source connected to areference potential, and set in the OFF state; and an output portionoutputting a reset signal when the potential of said internal nodedecreases below a threshold voltage after the application of a powersupply voltage to said power supply line.
 2. A power-on reset circuitaccording to claim 1, wherein said capacitor is a MOS capacitorcomprising a MOS transistor having its source and drain connected tosaid power supply line and its gate connected to said internal node.